Senior Lecturer in Embedded Systems

Deputy Director, Joint Programme Student Innovation Centre

Programme Lead, Internet of Things Engineering Programme (BUPT JP)

School of Electronic Engineering and Computer Science
Queen Mary University of London


Matthew Wai-Chung Tang finished his B.Eng in computer engineering, MPhil and PhD in computer science and engineering from the Chinese University of Hong Kong (CUHK) in 2003, 2005 and 2008 respectively.

He is a Senior Lecturer in Embedded Systems at the School of Electric Engineering and Computer Science (EECS), Queen Mary University of London (QMUL). He teaches regularly in the QMUL-BUPT Joint Programme (JP). Currently he is the Deputy Director of the JP Innovation Centre and the Programme Lead of the Internet of Things Engineering Programme. He received the Teaching Excellence Award from BUPT-QMUL Joint Programme in 2017/18.

Before joining QMUL, he was a Lecturer of the Department of Computer Science and Engineering (CSE) of CUHK. There he was honoured the Dean's Exemplary Teaching awards three times in 2010, 2011 & 2013.

His research interests include energy efficient computing architectures, reconfigurable computing and design automation algorithms for Field Programming Gate Arrays (FPGA). Matthew is the receipt of the Celoxica Best Paper Award in the 2007 IEEE Southern Conference on Programmable Logic (SPL'07) and the Best Presentation Award in 2007 International Ph.D. Workshop on SoC (IPS'07).

He is a Chartered Engineer, a fellow of Higher Education Academy (HEA) and a member of IET and IEEE.

Current Teaching in BUPT-QMUL Joint Programme

EBU5335: Digital System Design (Module Organiser 2015-2020)
EBU6475: Microprocessor System Design
EBU5476: Microprocessors for Embedded Design (Module Organiser 2014-present)

Current Teaching in EECS

ECS527U: Digital System Design (Module Organiser 2019-present)

Recent Publications


Tak-Kei Lam, Wai-Chung Tang, Xing Wei, Yi Diao, David Yu-Liang Wu, "Boolean Circuit Rewiring: Bridging Logical and Physical Designs", Wiley, ISBN: 978-1-118-75011-7, March 2016


Yu-Liang Wu, Wai Chung Tang, Lin Zhou, Wing Hang Lo, "Methods and systems for FPGA rewiring and routing in EDA designs", US Publication number US20090249276 A1, Oct 2009


T.K. Lam, W.C. Tang, X.Q. Yang, Y.L. Wu, "ECR: A Powerful and Low Complexity Error Cancellation Rewiring Scheme," to appear ACM Transactions on Design Automation of Electronic Systems (TODAES), 2012.

Haitong Tian, Wai-Chung Tang, Young, E.F.Y., Sze, C.N., "Postgrid Clock Routing for High Performance Microprocessor Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, no.2, pp.255-259, Feb. 2012


Wai-Chung Tang, "Reconfigurable Microcontroller for End Nodes in Internet of Things," IoT Ten-Cent System-on-Chip Challenge, Design Automation and Test in Europe (DATE) 2017

Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young, "A scalable routability-driven analytical placer with global router integration for FPGAs," FPGA 2014, pages 242

Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu, "Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire," VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on, pages 375-380, 5-9 Jan. 2014

Yi Diao, Wai-Chung Tang, Yu-Liang Wu, "An Effective SPFD-based Rewiring Scheme for FPGA Performance Improvement," 2013 International Conference on Electronic Engineering and Computer Science (EECS 2013), vol. 4, pp.216-223, 2013

Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff Sze and Charles Alpert, "Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths," Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific, pages 350-355, 2013

Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff Sze and Charles Alpert, "WRIP: Logic Restructuring Techniques for Wirelength-Driven Incremental Placement", GLSVLSI, pages 327-332, 2012.

Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu, "ECO Timing Optimization with Negotiation- Based Re-Routing and Logic Re-Structuring Using Spare Cells", in Proc. Asia and South Pacific Design Automation Conference, pp. 511-516, Jan 2012

L. Zhou, W. C. Tang, and Y. L. Wu, "Fast Placement-Intact Logic Perturbation Targeting for FPGA Performance Improvement", in Proc. IEEE Southern Conference on Programmable Logic (SPL 07), 2007, pp 63-68 | [Celoxica Best Paper Award].

Last updated: June 2021