Tak-Kei Lam, Wai-Chung Tang, Xing Wei, Yi Diao, David Yu-Liang Wu, "Boolean Circuit Rewiring: Bridging Logical and Physical Designs", Wiley, ISBN: 978-1-118-75011-7, March 2016
Yu-Liang Wu, Wai Chung Tang, Lin Zhou, Wing Hang Lo, "Methods and systems for FPGA rewiring and routing in EDA designs", US Publication number US20090249276 A1, Oct 2009
T.K. Lam, W.C. Tang, X.Q. Yang, Y.L. Wu, "ECR: A Powerful and Low Complexity Error Cancellation Rewiring Scheme," to appear ACM Transactions on Design Automation of Electronic Systems (TODAES), 2012.
Haitong Tian, Wai-Chung Tang, Young, E.F.Y., Sze, C.N., "Postgrid Clock Routing for High Performance Microprocessor Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, no.2, pp.255-259, Feb. 2012
Wai-Chung Tang, "Reconfigurable Microcontroller for End Nodes in Internet of Things," IoT Ten-Cent System-on-Chip Challenge, Design Automation and Test in Europe (DATE) 2017
Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young, "A scalable routability-driven analytical placer with global router integration for FPGAs," FPGA 2014, pages 242
Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu, "Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire," VLSI Design and 2014 13th International Conference on Embedded Systems, 2014 27th International Conference on, pages 375-380, 5-9 Jan. 2014
Yi Diao, Wai-Chung Tang, Yu-Liang Wu, "An Effective SPFD-based Rewiring Scheme for FPGA Performance Improvement," 2013 International Conference on Electronic Engineering and Computer Science (EECS 2013), vol. 4, pp.216-223, 2013
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff Sze and Charles Alpert, "Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths," Design Automation Conference (ASP-DAC), 2013 18th Asia and South Pacific, pages 350-355, 2013
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff Sze and Charles Alpert, "WRIP: Logic Restructuring Techniques for Wirelength-Driven Incremental Placement", GLSVLSI, pages 327-332, 2012.
Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu, "ECO Timing Optimization with Negotiation- Based Re-Routing and Logic Re-Structuring Using Spare Cells", in Proc. Asia and South Pacific Design Automation Conference, pp. 511-516, Jan 2012
L. Zhou, W. C. Tang, and Y. L. Wu, "Fast Placement-Intact Logic Perturbation Targeting for FPGA Performance Improvement", in Proc. IEEE Southern Conference on Programmable Logic (SPL 07), 2007, pp 63-68 | [Celoxica Best Paper Award].