Based on LLVM compiler and Z3 SMT Solver targeting ARM.

[LCGEN 0.0.1] planned release: summer 2017
A very preliminary prototype that relies on a simplistic homegrown specification of a small subset of ARMv7-A Instruction Set Architecture (ISA). This specification is partial, albeit sufficient by design for our microbenchmarks so far. It allowed us to carry out an early evaluation of our approach. We are encouraged to see that our prototype successfully handles some small but tricky examples used as standard benchmarks for other superoptimization and synthesis tools.